Work for wiring between integrated circuit packages, such as BGAs (ball grid arrays), on printed circuit boards (PCBs) and work for wiring inside integrated circuit packages are broadly divided into global routing and detailed routing. In global routing, between which pins each wire passes through and relative positional relationship of wires, and so on are determined. In detailed routing, actual wiring paths are determined based on the result of the global routing. Wiring paths created in the global routing are hereinafter referred to as “global paths”.
In wiring design in recent years, in order to achieve high-speed operations, nets for circuit devices having the same timing restriction are in many cases grouped into a single-layer bus (a bundle of nets) for connection therebetween. In terms of manufacturing costs, nets between components may be wired by a bus in order to efficiently use the wiring space and to suppress the number of layers needed for the wiring. Bus wiring is often applied to most of sections to be wired and it is increasingly becoming important to accurately estimate, at the stage of global routing, accommodation of bus wires.
One bus (a net group) typically has a few to about 64 nets or more. Global paths for bus wiring are not generally determined for individual nets belonging to a bus. In stead, for example, the width given by “the number of all bus nets”×(“wire width”+“wire spacing”) is generally used to determine a global path for a consolidated group, for example, with its start and end points being represented by the barycenter of a plurality of pins.
With the increased scales and increased densities of integrated circuits in recent years, a larger number of wiring layers is also needed for wiring design. An increase in the number of wires leads to an increase in the manufacturing cost. In order to minimize the number of wiring layers, it is necessary to optimize assignment of a global path of each bus to a layer, while considering a global path for another bus. For example, Japanese Laid-open Patent Publication No. 2009-301351 discloses a technology for determining, at the stage of the global routing, global paths and wiring layers for all buses while suppressing an increase in the number of layers used.
In the technology disclosed in Japanese Laid-open Patent Publication No. 2009-301351, however, there is a possibility that an appropriate result is not obtained unless the estimation accuracy of the area occupied by a net group (i.e., the bus) is appropriate. When an appropriate result is not obtained, the result affects the detailed design.
A major difficulty in the detailed routing lies in a portion where wires of the net group are extracted from a group of pins to the perimeter of a component. In that portion, the area that is usable for wires is very small, for example, for a few wires, and thus, if the area to be occupied by the net group is underestimated in the global routing, an unwired portion can remain. On the other hand, if the area to be occupied is overestimated, one or some net groups are crowded out to another layer that would otherwise be unnecessary.